Details
Title
Bonetti, Andrea
Sciper ID
227695
Affiliated labs
TCL
Publications
A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI
Circuits and Techniques for Dynamic Timing Monitoring in Microprocessors
DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment
ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories
FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters
GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI
Gain-Cell Embedded DRAMs: Modeling and Design Space
Low-Power Design of Digital VLSI Circuits around the Point of First Failure
See complete list of publications (25)
Circuits and Techniques for Dynamic Timing Monitoring in Microprocessors
DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment
ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories
FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters
GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI
Gain-Cell Embedded DRAMs: Modeling and Design Space
Low-Power Design of Digital VLSI Circuits around the Point of First Failure
See complete list of publications (25)
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