Notice détaillée
Titre
Athanasopoulos, Panagiotis
Sciper ID
175458
Publications
3D configuration caching for 2D FPGAs
3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling
A 3D Stacked Multi-Core Processor Platform with Improved Testability
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs
Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology
Towards Multi-Fabric 3D Integration Architectures
3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling
A 3D Stacked Multi-Core Processor Platform with Improved Testability
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs
Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology
Towards Multi-Fabric 3D Integration Architectures
Employé pour
Athanasopoulos, P
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