Details
Title
Kull, Lukas
Sciper ID
197929
Affiliated labs
LSM
Publications
A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS
A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
A 24-to-72GS/s 8b Time-Interleaved SAR ADC with 2.0-to-3.3pJ/conversion and > 30dB SNDR at Nyquist in 14nm CMOS FinFET
A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS
A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS
A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS
An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels
Energy-Efficient High-Speed SAR ADCs in CMOS
Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
See complete list of publications (15)
A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
A 24-to-72GS/s 8b Time-Interleaved SAR ADC with 2.0-to-3.3pJ/conversion and > 30dB SNDR at Nyquist in 14nm CMOS FinFET
A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS
A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS
A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS
An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels
Energy-Efficient High-Speed SAR ADCs in CMOS
Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
See complete list of publications (15)
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