Notice détaillée
Titre
Beretta, Ivan
Sciper ID
196973
Laboratoires affiliés
ESL
Publications
A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design
A Wireless Body Sensor Network For Activity Monitoring With Low Transmission Overhead
Design Exploration of Energy-Performance Trade-offs for Wireless Sensor Networks
Design Methodologies for Application-Oriented Embedded Systems Under Variable Performance/Constraints Tradeoffs
Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes
Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes
Knowledge-based design space exploration of wireless sensor networks
Parallelizing the Chambolle Algorithm for Performance Optimized Mapping on FPGA devices
Voir toutes les publications (18)
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design
A Wireless Body Sensor Network For Activity Monitoring With Low Transmission Overhead
Design Exploration of Energy-Performance Trade-offs for Wireless Sensor Networks
Design Methodologies for Application-Oriented Embedded Systems Under Variable Performance/Constraints Tradeoffs
Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes
Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes
Knowledge-based design space exploration of wireless sensor networks
Parallelizing the Chambolle Algorithm for Performance Optimized Mapping on FPGA devices
Voir toutes les publications (18)
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