Experimental g(m)/I-D Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Transconductance efficiency (g(m)/I-D) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of g(m)/I-D versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully depleted MOSFET. This paper studies the breakdown of this invariance versus back-gate voltage, transistor length, temperature, drain-to-source voltage, and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28-nm ultra-thin body and box fully depleted Silicon-on-Insulator (SOI) (FDSOI) CMOS technology, thus supporting the g(m)/I-D-based design methodologies usage in DG FDSOI transistors sizing.


Publié dans:
Ieee Transactions On Electron Devices, 65, 1, 11-18
Année
2018
Publisher:
Piscataway, Ieee-Inst Electrical Electronics Engineers Inc
ISSN:
0018-9383
Mots-clefs:
Laboratoires:




 Notice créée le 2018-01-15, modifiée le 2018-01-28


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