Hierarchical Reversible Logic Synthesis Using LUTs

Today's rapid advances in the physical implementation of quantum computers demand for scalable synthesis methods in order to map practical logic designs to quantum architectures. We present a synthesis algorithm for quantum computing based on k-LUT networks, which can be derived from Verilog netlists using state-of-the-art and of-the-shelf mapping algorithms. We demonstrate the effectiveness of our method in automatically synthesizing several floating point networks up to double precision. As many quantum algorithms target scientific simulation applications, they can make rich use of floating point arithmetic components. But due to the lack of quantum circuit descriptions for those components, it is not possible to find a realistic cost estimation for the algorithms. Our synthesized benchmarks provide cost estimates that allow quantum algorithm designers to provide the first complete cost estimates for a host of quantum algorithms. This is an essential step towards the goal of understanding which quantum algorithms will be practical in the first generations of quantum computers.


Published in:
Proceedings of the 54th ACM/IEEE Design Automation Conference (DAC)
Presented at:
54th ACM/IEEE Design Automation Conference (DAC), Austin, Texsas, USA, 18-22 June 2017
Year:
Jun 22 2017
Publisher:
IEEE
ISBN:
978-1-4503-4927-7
Note:
ERC Cybercare 669354 / SNF MAJesty 200021-169084 / ICT COST Action IC1405
Laboratories:


Note: The status of this file is: EPFL only


 Record created 2018-01-09, last modified 2018-09-13

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