RM3 based logic synthesis

In-memory computing devices, such as resistive RAMs, natively implement material implication or a variant of the majority-of-three operation called RM<sub>3</sub>. This operation generalizes material implication and has been used as target operation in several logic synthesis algorithms for in-memory computing applications. In this work, we investigate a homogeneous logic network data structure that uses RM<sub>3</sub> as only logic operation. Such a data structure makes an ideal fit for the use in design automation algorithms for in-memory computing. We show how to derive RM<sub>3</sub> networks from well-known logic synthesis data structures and a technique how to obtain such networks using technology mapping.


Publié dans:
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
Présenté à:
IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, Maryland, USA, May 28-31, 2017
Année
May 31 2017
Publisher:
IEEE
ISBN:
978-1-4673-6853-7
Mots-clefs:
Note:
ERC Cybercare 669354 / SNF MAJesty 200021-169084 / SNF 200021-146600
Laboratoires:


Note: Le statut de ce fichier est: Seulement EPFL


 Notice créée le 2018-01-09, modifiée le 2019-03-17

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