conference paper
A parallel low-complexity coefficient computation processor for the MMSE decision feedback equalizer
1997
Proceedings on the 31st Asilomar Conference on Signals, Systems, and Computers
A modular parallel architecture for a MMSE-DFE coefficient computation processor is presented. The architecture is based on the QR factorization of a channel-and-noise-dependent data matrix and is implemented using CORDIC processors within a systolic array architecture. Implementation issues including the number of CORDIC stages and the bit precision required in a fixed-point implementation are investigated through computer simulations.
Type
conference paper
Author(s)
Al-Dahir, N.
Date Issued
1997
Published in
Proceedings on the 31st Asilomar Conference on Signals, Systems, and Computers
Start page
1586
End page
1590
Editorial or Peer reviewed
REVIEWED
Written at
OTHER
EPFL units
| Event name | Event place | Event date |
Pacific Grove, CA, USA | November 2-5, 1997 | |
Available on Infoscience
January 4, 2018
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