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research article
Clock Jitter Compensation in High-Rate ADC Circuits
Clock timing jitter refers to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acquired samples in the midst of random noise. We propose low-complexity digital signal processing methods for estimating the jitter in real-time for direct downconversion receivers at high sampling rates. We also propose adaptive compensation methods for the jitter and analyze the performance of the proposed techniques in some detail as well as through simulations.
Type
research article
Authors
Publication date
2012
Publisher
Published in
Volume
60
Issue
11
Start page
5738
End page
5753
Peer reviewed
REVIEWED
EPFL units
Available on Infoscience
December 19, 2017
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