Research and development efforts on chip and wafer-scale 3D integration for system miniaturization have been continuing for more than a decade. However, there are still only a handful of 3D integrated products available in the market due to the high cost and complexity of the integration processes. Another issue is the increased difficulty of integrating more than 2 layers due to the inherent limitations in most processes. It is thus evident that the development of alternative techniques which are simpler, more cost-effective and can go beyond the second level is needed to advance the field. The main objective of this thesis is to develop low-cost and simple copper TSV- based processes for homogeneous and heterogeneous integration platforms, presenting a new path to achieve system miniaturization for high performance, high bandwidth, and low power consumption. In the first part of this thesis, a process developed for multi-layer integration of CMOS flash memory chips is presented. Multi-layer integration has been achieved in a step-by-step manner where first a 2-layer integration process flow mostly compatible with iterative use has been developed and then improvements and modifications allowed it to be implemented for multi-layer integration. The technologies used can be summarized as: i) IBE and DRIE for TSV formation, ii) Adhesive thermo-compression bonding with Parylene-C, iii) Copper electroplating for TSV filling. The improved process protocol for multi-layer integration includes several enhancements such as a strengthened parylene layer, pseudo-tapered via structures and gradual electrodeposition. Successfully fabricated 4-layer stacks have been successfully packaged in SEC packages by the collaborator, which also shows the compatibility of the process with commercial packaging lines. Resistance characterizations produced a single TSV resistance of 180 m¿ for CMOS memory chips. Moreover, TDR measurements performed on packaged samples produced an average inductance value of 0.9 nH for 3D-integrated stacks whereas this value is 1.5 nH for wire-bonded stacks, showing the improved impedance characteristics after 3D integration, which in turn results in a higher signal integrity. The second part of the thesis presents the development of a chip-to-wafer heterogeneous integration process using Parylene-C with improved hydrophobicity. Chip-to-wafer integration provides much higher flexibility since it allows samples of different sizes and surface properties to be integrated while still having a much higher throughput than chip-to-chip integration. A novel method has been developed to use surface tension-driven self-alignment for integrating multiple chips on a wafer, where a modified parylene layer with enhanced hydrophobicity has been used to confine the top chips on target locations. Sample bottom wafers and top chips have been fabricated and successfully integrated using the developed technique. Wafer-level misalignment measurements produced a mean alignment error of 4.2 µm with a standard deviation of 1.5 µm, showing that the developed technique is suitable for applications which do not require high resolutions, while also allowing heterogeneous integration to be performed in non-CMOS-grade cleanrooms without using automated special tools.