Infoscience

Thesis

Design Techniques for Ultra High Frequency Clock Generation in 28 nm FDSOI Technology

Twentieth century has been the golden age of semiconductor industry by achieving a high level of growth as a courtesy of developments in fabrication techniques and downscaling of the technology. Since the downscaling in current lithography technology is reaching its limits, it becomes harder to keep up with the Moore's Law. Hence, the industry shifts its focus to More-than-Moore approach that is diversifying the functionalities integrated on the chip. In this new era, FDSOI technology draws attention thanks to its analog/RF friendly structure, body-tuning feature and economic advantage compared to its competitors. Despite these advantages, analog/mixed-signal design suffers from reduced supply voltage, leakage and insufficient signal integrity in this technology. Therefore, designers need new design approaches to combat these issues. Towards this aim, working on ultra high frequency clock generation is suitable since it is a true analog/mixed-signal design question with possible architectures composing of analog and digital blocks. Moreover, high speed clock generation is essential in a range of applications including mobile communications, microprocessors and memories. Although the intrinsic speed of the transistors has increased significantly in the state-of-the-art processes, the clock frequencies have not reached this high level due to physical limitations. Parallelism can surpass this constraint. It has gained popularity especially in time-interleaved (TI) ADCs. These TI systems require multi-phase clock signals. Hence, ultra high frequency clock generation with multiple phases is an attractive research topic. The goal of this thesis is to determine the performance limits for ultra high frequency multi-phase clock generators in 28 nm FDSOI process and explore the potential of this technology in solving the challenges of analog/mixed-signal design. In order to fulfil these purposes, two chips have been fabricated. The first one demonstrates an 8-phase 7.51 GHz to 8.38 GHz body-tuned ring oscillator (VCO) with less than 4% KVCO variation over its tuning voltage range. The circuit exhibits a frequency tuning range of 870 MHz with a very linear KVCO of 484 MHz/V. The oscillator consumes 4 mW and the measured phase noise is -77.44 dBc/Hz at a 1 MHz offset from a 8.38 GHz center frequency. Dual-core and quad-core versions of the VCO are also tested. The output frequency of the dual-core VCO is from 6.72 GHz to 7.51 GHz with a tuning range of 790 MHz and a KVCO of 439 MHz/V. And, the output frequency of the quad-core VCO is from 6.53 GHz to 7.06 GHz with a tuning range of 530 MHz and a KVCO of 295 MHz/V. The second chip incorporates a highly-programmable frequency synthesizer whose core block is a third-order charge-pump PLL that uses the same VCO as the first chip. The PLL is enriched with digital circuitry solutions and a charge pump using a body-driven comparator. The programmability allows controlling the stability, loop bandwidth and output noise. The measurement results show that the PLL can synthesize frequencies from 7.2 GHz to 7.76 GHz. The whole system consumes 15.78 mW and the measured phase noise is -85.14 dBc/Hz at 1 MHz offset from 7.44 GHz center frequency. At the same frequency, the resulting minimum jitter is 5.65 ps. To the best of author's knowledge, these chips are the first FDSOI silicon demonstrations of a body-tuned high frequency ring oscillator with linear tuning characteristics and its integration into a PLL.

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