A Hybrid CDAC-Threshold Configuring SAR ADC in 28nm FDSOI CMOS

In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The proposed architecture implements binary search through a redundant capacitive DAC for the 5 first MSBs and through programmable comparator thresholds for the remaining 4 LSBs. The DAC capacitance at the front-end remains small enough to achieve high sampling rate with increased input bandwidth. Two asynchronously clocked alternate comparators are used additionally to improve conversion speed. The ADC is designed and simulated in 28nm FD-SOI CMOS. It consumes 4.1 mW from a 1V supply, while achieving a SNDR of 52.1 dB and a Figure-of-Merit of 11.4 fJ/conversion-step.

Presented at:
IEEE International New Circuits and Systems Conference (NEWCAS), Strasbourg, France, June 25-28, 2017

 Record created 2017-06-27, last modified 2018-09-13

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