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patent
Controllable polarity fet based arithmetic and differential logic
Amaru, Luca Gaetano
•
Gaillardon, Pierre-Emmanuel Julien Marc
•
De Micheli, Giovanni
2014
A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=AB+BC+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output.
Type
patent
EPO Family ID
46800022
Inventors
Amaru, Luca Gaetano
•
Gaillardon, Pierre-Emmanuel Julien Marc
•
De Micheli, Giovanni
TTO classification
TTO:6.1192
EPFL units
Patent number | Country code | Kind code | Date issued |
US9130568 | US | B2 | 2015-09-08 |
US2014043060 | US | A1 | 2014-02-13 |
Available on Infoscience
May 24, 2017
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