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  4. Unified prefetching into instruction cache and branch target buffer
 
patent

Unified prefetching into instruction cache and branch target buffer

Falsafi, Babak  
•
Kaynak, Ilknur Cansu  
•
Grot, Boris Robert  
2017

A system and method of coupling a Branch Target Buffer (BTB) content of a BTB with an instruction cache content of an instruction cache. The method includes: tagging a plurality of target buffer entries that belong to branches within a same instruction block with a corresponding instruction block address and a branch bitmap to indicate individual branches in the block; coupling an overflow buffer with the BTB to accommodate further target buffer entries of instruction blocks, distinct from the plurality of target buffer entries, which have more branches than the bundle is configured to accommodate in the corresponding instruction's bundle in the BTB; and predicting the instructions or the instruction blocks that are likely to be fetched by the core in the future and fetch those instructions from the lower levels of the memory hierarchy proactively by means of a prefetcher.

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Type
patent
EPO Family ID

58409547

Author(s)
Falsafi, Babak  
Kaynak, Ilknur Cansu  
Grot, Boris Robert  
TTO classification

TTO:6.1468

EPFL units
AVP-R-TTO  
PARSA  
DOICountry codeKind codeDate issued

US9996358

US

B2

2018-06-12

US2017090935

US

A1

2017-03-30

Available on Infoscience
May 2, 2017
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/136982
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