Through silicon vias (TSVs) are key enablers of 3-D integration technologies which, by vertically stacking and interconnecting multiple chips, achieve higher performances, lower power, and a smaller footprint. Copper is the most commonly used conductor to fill TSVs; however, copper has a high thermal expansion mismatch in relation to the silicon substrate. This mismatch results in a large accumulation of thermomechanical stress when TSVs are exposed to high temperatures and/ or temperature cycles, potentially resulting in device failure. In this paper, we demonstrate 300 mu m long, 7:1 aspect ratio TSVs with Invar as a conductive material. The entire TSV structure can withstand at least 100 thermal cycles from -50 degrees C to 190 degrees C and at least 1 h at 365 degrees C, limited by the experimental setup. This is possible thanks to matching coefficients of thermal expansion of the Invar via conductor and of silicon substrate. This results in thermomechanical stresses that are one order of magnitude smaller compared to copper TSV structures with identical geometries, according to finite element modeling. Our TSV structures are thus a promising approach enabling 2.5-D and 3-D integration platforms for hightemperature and harsh-environment applications.