Optimization Opportunities in RRAM-based FPGA Architectures

<i>Static Random Access Memory</i> (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures typically avoiding the use of large multiplexers. <i>Resistive Random Access Memory</i> (RRAM)- based multiplexers, built with one-level structure, have a unique advantage over SRAM-based multiplexers: their ideal delay is independent from the input size. This property allows RRAM-based FPGA architectures to use larger multiplexers than their SRAM-based counterparts, without generating any delay overhead. In this paper, by carefully considering the properties of RRAM multiplexers, we assess that current state-of-art architectural parameters for SRAM-based FPGAs cannot preserve optimality in the context of RRAM-based FPGAs. As a result, we propose that in RRAM-based FPGAs, (a) the routing tracks should be interconnected to <i>Look-Up Table</i> (LUT) inputs via a one-level crossbar, instead of through <i>Connection Blocks</i> and local routing; (b) the <i>Switch Blocks</i> should employ larger multiplexers; (c) length-2 wires should be used instead of length-4 wires. When operated in nominal voltage, the proposed RRAM-based FPGA architecture reduces area by 26%, delay by 39% and channel width by 13%, as compared to a SRAM-based FPGA with a classical architecture. When operated in the near-Vt regime, the proposed RRAM-based FPGA architecture improves <i>Area-Delay Product</i> by 42% and <i>Power-Delay Product</i> by 5x as compared to a classical SRAM-based FPGA at nominal voltage.

Published in:
Proceedings of the IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS)
Presented at:
IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), Bariloche, Argentina, February 20-23, 2017
New York, IEEE

 Record created 2017-02-28, last modified 2019-03-17

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