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conference paper
Hardware Decoders for Polar Codes: An Overview
2016
2016 Ieee International Symposium On Circuits And Systems (Iscas)
Polar codes are an exciting new class of error correcting codes that achieve the symmetric capacity of memoryless channels. Many decoding algorithms were developed and implemented, addressing various application requirements: from error-correction performance rivaling that of LDPC codes to very high throughput or low-complexity decoders. In this work, we review the state of the art in polar decoders implementing the successive-cancellation, belief propagation, and list decoding algorithms, illustrating their advantages.
Type
conference paper
Web of Science ID
WOS:000390094700038
Authors
•
Sarkis, Gabi
•
Balatsoukas-Stinning, Alexios
•
Fan, Youzhe
•
Tsui, Chi-Ying
•
•
Thibeault, Claude
•
Gross, Warren J.
Publication date
2016
Publisher
Published in
2016 Ieee International Symposium On Circuits And Systems (Iscas)
ISBN of the book
978-1-4799-5341-7
Publisher place
New York
Total of pages
4
Series title/Series vol.
IEEE International Symposium on Circuits and Systems
Start page
149
End page
152
Peer reviewed
REVIEWED
EPFL units
Event name | Event place | Event date |
Montreal, CANADA | MAY 22-25, 2016 | |
Available on Infoscience
January 24, 2017
Use this identifier to reference this record