This paper presents constraints involved in the microelectronic implementation of a transmission line model based on transconductor-capacitor (gm-C) topologies. The presented line model, based on the discretization of a transmission line into a finite number of series inductors and shunt capacitors, is aimed for the fault location in power network, a technique using the Electromagnetic Time-Reversal (EMTR) principle. The discrete LC line behavior is simulated by gm-C circuits, more suitable for integration. This research exposes design limitations in term of transconductor non-linearities, finite common mode voltage amplification and offset, and shows how they impact the line model and the fault location method accuracy. According to the analysis, corresponding design constraints on the gm-C line model are deduced in order to reach a fault location resolution of 1%, while preserving a short processing time, inherent to the method, in comparison to classical methods.