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  4. High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology
 
conference paper

High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology

Jansen, R. J. E.
•
Lindner, S.
2016
Esscirc Conference 2016
46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC)

The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus minimising any hot carrier injection and dielectric stress degradation. The presented voltage extension technique is scalable to larger and smaller external voltages and suitable for all twin-well technology feature sizes. The technique using the cascade of complementary latches is applied to the realization of a CAN output driver in a digital twin-well double-oxide 180nm technology featuring both 1.8V 180nm and 3.3V 350nm CMOS devices. The CAN driver consists of two bi-state drivers, which are both in high-impedance state during the CAN recessive state and in the high and respectively low state for the CAN dominant state. The realized prototype driver can handle external voltages between -3V and 16V and exhibits a 1.5V differential output swing on a 60Ohm load over the military temperature range compliant to the CAN automotive standard. To the best of our knowledge this is also the first realization of a CAN driver in a low-voltage digital CMOS technology.

  • Details
  • Metrics
Type
conference paper
DOI
10.1109/ESSCIRC.2016.7598297
Web of Science ID

WOS:000386656300068

Author(s)
Jansen, R. J. E.
Lindner, S.
Date Issued

2016

Publisher

Ieee

Publisher place

New York

Published in
Esscirc Conference 2016
ISBN of the book

978-1-5090-2972-3

Total of pages

4

Series title/Series vol.

Proceedings of the European Solid-State Circuits Conference

Start page

281

End page

284

Subjects

Buffer circuits

•

CMOS integrated circuits

•

high-voltage techniques

•

Control Area Network

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
IMT  
Event nameEvent placeEvent date
46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC)

Lausanne, SWITZERLAND

SEP 12-15, 2016

Available on Infoscience
January 24, 2017
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/133430
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