Analysis of Substrate Currents Propagation in HVCMOS technology

This work reports the results of a layout-aware substrate modeling methodology for HVCMOS technologies. The model relies on the extraction of parasitic substrate network to simulate with circuit software parasitic lateral NPN bipolar transistors with multi-collector configuration. This allows to predict and analyze the injected substrate currents distribution through the chip and to explore different layout strategies to reduce the propagation of minority carriers through the substrate. Simulations results show good agreement in comparison with measurements at different temperatures.


Published in:
2016 46th European Solid-State Device Research Conference (ESSDERC), 319-322
Presented at:
46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, Switzerland, September 12-15, 2016
Year:
2016
Publisher:
New York, IEEE
ISBN:
978-1-5090-2969-3
Keywords:
Laboratories:




 Record created 2017-01-24, last modified 2018-09-13


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)