Busy Man’s Synthesis: Combinational Delay Optimization With SAT

Boolean SAT solving can be used to find a minimum- size logic network for a given small Boolean function. This paper extends the SAT formulation to find a minimum-size network under delay constraints. Delay constraints are given in terms of input arrival times and the maximum depth. After integration into a depth-optimizing mapping algorithm, the proposed SAT formulation can be used to perform logic rewriting to reduce the logic depth of a network. It is shown that to be effective the logic rewriting algorithm requires (i) a fast SAT formulation and (ii) heuristics to quickly determine whether the given delay constraints are feasible for a given function. The proposed algorithm is more versatile than previous algorithms, which is confirmed by the experimental results.


Published in:
Proceedings of the Design, Automation & Test in Europe (DATE)
Presented at:
Design, Automation & Test in Europe (DATE), Lausanne, Switzerland, March 27-31, 2017
Year:
Mar 31 2017
Publisher:
New York, Ieee
ISBN:
978-3-9815370-9-3
Note:
ERC Cybercare 669354 / SNF MAJesty 200021-169084 / NSF-NSA Uni Berkeley
Laboratories:




 Record created 2017-01-10, last modified 2018-09-13

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