TY - CPAPER
AB - Boolean SAT solving can be used to find a minimum- size logic network for a given small Boolean function. This paper extends the SAT formulation to find a minimum-size network under delay constraints. Delay constraints are given in terms of input arrival times and the maximum depth. After integration into a depth-optimizing mapping algorithm, the proposed SAT formulation can be used to perform logic rewriting to reduce the logic depth of a network. It is shown that to be effective the logic rewriting algorithm requires (i) a fast SAT formulation and (ii) heuristics to quickly determine whether the given delay constraints are feasible for a given function. The proposed algorithm is more versatile than previous algorithms, which is confirmed by the experimental results.
T1 - Busy Manâ€™s Synthesis: Combinational Delay Optimization With SAT
DA - 2017-03-31
AU - Soeken, Mathias
AU - De Micheli, Giovanni
AU - Mishchenko, Alan
JF - Proceedings of the Design, Automation & Test in Europe (DATE)
PB - Ieee
PP - New York
N1 - ERC Cybercare 669354 / SNF MAJesty 200021-169084 / NSF-NSA Uni Berkeley
ID - 224352
SN - 978-3-9815370-9-3
UR - http://infoscience.epfl.ch/record/224352/files/2017_date_2.pdf
ER -