Physical Design Considerations of One-level RRAM-based Routing Multiplexers

<i>Resistive Random Access Memory</i> (RRAM) technology opens the opportunity for granting both high-performance and low- power features to routing multiplexers. In this paper, we study the physical design considerations related to RRAM- based routing multiplexers and particularly the integration of 4T(ransistor)1R(RAM) programming structures within their routing tree. We first analyze the limitations in the physical design of a naive one-level 4T1R-based multiplexer, such as co-integration of low-voltage nominal power supply and high voltage programming supply, as well as the use of long metal wires across different isolating wells. To address the limitations, we improve the one-level 4T1R-based multiplexer by re-arranging the nominal and programming voltage domains, and also study the optimal location of RRAMs in terms of performance. The improved design can effectively reduce the length of long metal wires by 50%. Electrical simulations show that using a 7nm FinFET transistor technology, the improved 4T1R-based multiplexers improve delay by 69% as compared to the basic design. At nominal working voltage, considering an input size ranging from 2 to 32, the improved 4T1R-based multiplexers outperform the best CMOS multiplexers in area by 1.4×, delay by 2× and power by 2× respectively. The improved 4T1R-based multiplexers operating at near-Vt regime can improve <i>Power-Delay Product</i> by up to 5.8× when compared to the best CMOS multiplexers working at nominal voltage.

Published in:
Proceedings of the International Symposium on Physical Design (ISPD)
Presented at:
ACM International Symposium on Physical Design (ISPD), Portland, Oregon, USA, March 19-22, 2017
New York, New York, USA, ACM

 Record created 2017-01-10, last modified 2020-07-29

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