Multi-level Logic Benchmarks: An Exactness Study

In this paper, we study exact multi-level logic benchmarks. We refer to an exact logic benchmark, or exact benchmark in short, as the optimal implementation of a given Boolean function, in terms of minimum number of logic levels and/or nodes. Exact benchmarks are of paramount importance to design automation because they allow engineers to test the efficiency of heuristic techniques used in practice. When dealing with two-level logic circuits, tools to generate exact benchmarks are available, e.g., <i>espresso-exact</i>, and scale up to relatively large size. However, when moving to modern multi-level logic circuits, the problem of deriving exact benchmarks is inherently more complex. Indeed, few solutions are known. In this paper, we present a scalable method to generate exact multi-level benchmarks with the optimum, or provably close to the optimum, number of logic levels. Our technique involves concepts from graph theory and joint support decomposition. Experimental results show an asymptotic exponential gap between state-of- the-art synthesis techniques and our exact results. Our findings underline the need for strong new research in logic synthesis.

Published in:
Proceedings of the 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Presented at:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, January 16-19, 2017
New York, Ieee

 Record created 2017-01-10, last modified 2018-03-17

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