Orthogonal differential vector signaling codes with embedded clock

Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.


Year:
2016
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EPO Family ID: 55181167
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 Record created 2016-12-15, last modified 2018-03-17

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