26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology

The continuing demand for higher bandwidth in serial interconnects has pushed the symbol rate of differential lanes into the high-insertion-loss region of channels. Multi-level signaling such as differential PAM-4 [1] has been used to mitigate the loss of electrical channels by lowering the signal spectrum. Such an approach suffers from lower SNR tolerance as well as higher susceptibility to crosstalk and ISI as compared to differential signaling (DS). Coded differential approaches have been reported [2] to mitigate ISI. Our approach is a generalization of DS in which ternary values are transmitted on an 8-wire bus. The set of transmitted values belongs to a code consisting of 256 code-words called the 8b8w-code (8-bits-on-8-wires) [3]. The specific correlations in the code-words of the 8b8w-code eliminate transmit common-mode and simultaneous switching output (SSO) noise and allow for detection via self-referencing comparators (unlike PAM-4), which provides additional noise immunity. Compared to DS, the 8b8w-code offers twice the throughput at 50% of the line power. Compared to PAM-4, the code offers better SNR (3dB) at 38% of the line power with enhanced tolerance of ISI and lower crosstalk generation. The design and experimental verification of an 8b8w transceiver in 40nm CMOS is described. Transmission is achieved up to 12Gb/s per wire over 55cm of Rogers with up to 15dB loss.


Published in:
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Presented at:
IEEE Solid State Circuits Conference, San Francisco, USA, February 9-13, 2014
Year:
2014
ISBN:
978-1-4799-0920-9
Keywords:
Note:
Received the ISSCC Jan van Vessem Award
Laboratories:




 Record created 2016-11-23, last modified 2018-09-13

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