Double-Gate Negative-Capacitance MOSFET with PZT gate stack on Ultra-Thin Body SOI: an Experimentally Calibrated Simulation Study of Device Performance

In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain negative capacitance effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure realistic simulation results. The ferroelectric thickness obtained by the proposed approach leads to the maximum enhancement in the non-hysteretic operation of negative capacitance transistors. We report a clear and significant double improvement in (i) subthreshold swing and (ii) gate overdrive, using negative capacitance effect. Simulations using Silvaco TCAD coupled with a realistic Landau model of ferroelectrics demonstrates that a 14nm node UTBB FDSOI-FET can operate at 0.26V instead of 0.9V gate voltage using negative capacitance effect, with an average subthreshold swing of 55mV/decade at room temperature. The double gate structure is proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the negative capacitance effect and reduce the ferroelectric’s optimized thickness. A 14nm node DG-NCFET can operate at 0.24V gate voltage with an average subthreshold swing of 45mV/decade.

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IEEE Transactions on Electron Devices, 63, 12, 4678-4684

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 Record created 2016-10-16, last modified 2020-10-28

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