A Sub-0.5 Electron Read Noise VGA Image Sensor in a Standard CMOS Process

• Published in: IEEE Journal of Solid-State Circuits, vol. 51, num. 9, p. 2180-2191
• Piscataway: Ieee-Inst Electrical Electronics Engineers Inc, 2016

A sub-0.5e−rms temporal read noise VGA (640H×480V) CMOS image sensor has been integrated in a standard 0.18μm 4PM CMOS process. The low noise performance is achieved exclusively through circuit optimization without any process refinements. The presented imager relies on a 4T pixel of 6.5μm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. With a pixel bias of 1.5μA the sensor chip features an input-referred noise histogram from 0.25 e−rms to a few e−rms peaking at 0.48 e−rms. The imager features a full well capacity of 6400 e− and its frame rate can go up to 80 fps. It also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6e-/s. It is also shown that the implementation of the in-pixel n-well does not impact the quantum efficiency of the pinned photo-diode.

Keywords: CMOS ; CIS ; image sensor ; low noise ; sub-electron ; low light ; 1 / f noise ; thermal noise ; thin oxide ; thick oxide

Reference

• EPFL-ARTICLE-218991
• doi:10.1109/JSSC.2016.2579643
• View record in Web of Science

Record created on 2016-07-01, modified on 2017-05-10