Inversion optimization in majority-inverter graphs

Many emerging nanotechnologies realize majority gates as primitive building blocks and they benefit from a majority-based synthesis. Recently, <i>Majority-Inverter Graphs</i> (MIGs) have been introduced to abstract these new technologies. We present optimization techniques for MIGs that aim at rewriting the complemented edges of the graph without changing its shape. We demonstrate the performance of our optimization techniques by considering three cases of emerging technology design: semi-custom digital design using <i>Spin Wave Devices</i> (SWDs) and <i>Quantum-Dot Cellular Automata</i> (QCA); and logic in-memory operation within <i>Resistive Random Access Memories</i> (RRAMs). Our experimental results show that SWD and QCA technologies benefit from complemented edges minimization. Area, delay, and power of SWD-based circuits are improved by 13.8%, 21.1%, and 9.2% respectively, while the number of QCA cells in QCA-based circuits can be decreased by 4.9% on average. Reductions of 14.4% and 12.4% in the number of devices and sequential steps respectively can be achieved for RRAMs when the number of nodes with exactly one complemented input is increased during MIG optimization.


Published in:
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 15-20
Presented at:
IEEE/ACM International Symposium on Nanoscale Archituectures (NANOARCH), Beijing, China, July 18-20, 2016
Year:
Jun 15 2016
Publisher:
New York, Ieee
ISBN:
978-1-4503-4330-5
Note:
ERC Cybercare 669354 / SNF 200021-146600
Laboratories:




 Record created 2016-06-21, last modified 2018-09-13

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