DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28nm FD-SOI technology show that DynOR provides an average speedup of 19% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15%, compared to a static clocking scheme based on worst case excitation.


Published in:
Esscirc Conference 2016, 261-264
Presented at:
42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, Switzerland, September 12-15, 2016
Year:
2016
Publisher:
New York, Ieee
ISSN:
1930-8833
ISBN:
978-1-5090-2972-3
Keywords:
Laboratories:




 Record created 2016-06-13, last modified 2018-03-17

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