Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of concern and enables a tradeoff between different architectures with respect to the analog input bandwidth, the hold time of the sampled signal, and constraints on the clock path. The two ADCs at 6 and 8 b resolution implement inline demux sampling with 32× and 64× interleaving to achieve 36 GS/s at 110 mW and 90 GS/s at 667 mW, respectively. The analog input bandwidth of both ADCs exceeds 20 GHz. The SNDR of the 64× interleaved ADC is above 36 dB up to 6.1 GHz and above 33 dB up to 19.9 GHz at 90 GS/s, and the SNDR of the 32× interleaved ADC exceeds 31.6 dB up to Nyquist at 36 GS/s. The 32×and 64× interleaved ADCs are optimized for area and occupy 0.048 and 0.45 mm2, respectively, in 32 nm CMOS SOI technology.
Keywords: Analog-to-digital converter (ADC) ; successive approximation (SAR) ; 100 GBE ; interleaver ; time-interleaved ; sampling ; bandwidth model ; inline demux ; asynchronous ; alternate comparators.
Record created on 2016-06-09, modified on 2016-08-09