The evolution and characteristics of the electronics is directly linked to the technological and societal progress. Today, there is a huge variety of electronic solutions offered, with the RF low-power systems, such as wireless sensor networks, wireless body area networks and the Internet of Things (IoT), to gain more and more ground. However, these RF low-power applications set stringent constraints on the power consumption, which complicate even more the already difficult task of the RF IC design. This can be addressed by exploiting the phenomenal RF performance offered by the state-of-the-art nanoscale CMOS technologies, with impressive peak transit frequency at the order of hundreds of GHz, and sub-1 dB minimum noise figure. More specifically, most of the RF applications operate at the low GHz range, so the cut-off frequency surplus, achieved typically in strong-inversion (SI), can be traded-off with a lower power consumption by shifting the operating point to moderate- (MI) or weak-inversion (WI), while keeping the RF performance within the desired specifications. There is an extensive work by the semiconductor community on characterization and modeling the MOS transistor at RF. Nonetheless, most of such studies focus either on the high-performance SI or on rather mature processes with respect to the contemporary state-of-the-art. In this thesis, an extensive and multi-faceted work on detailed characterization and accurate modeling of nanoscale MOSFETs for low-power operation, focusing therefore on subthreshold operation, is presented and discussed. The analysis is always performed under the perspective of the ultra-low power RF IC design. After all, the reliability of the RF IC simulation tools in this high-end range of frequencies and at very low current densities, which constitute the two extreme conditions in terms of operation of the transistor, strongly depends on the accuracy of the model used. The dissertation follows a dual course. First, a simple, yet thorough, small-signal RF model is elaborated in order, to describe analytically the RF performance of nanoscale MOSFETs from SI down to the deep WI region, including its noise behavior. Further, the analytical expressions are used in order to form a step-by-step parameter extraction methodology. Especially, for the extraction of the RF noise model parameters, an innovative step-by-step procedure, which is applied directly on measurements, is developed. Then, a state-of-the-art physics-based compact model (BSIM6) is used. Within this part of the work, a set of novel advancements and contributions are introduced in order for the model to be able to capture the complexity of the behavior of modern advanced CMOS technologies. The results show excellent agreement regarding all different aspects, across all modes of operation (CV, DC, RF performance), even at very low bias conditions. The evaluation of both the modeling approaches is done in detail and uses design oriented tools and metrics, such as the Gm/ID, the Y-parameters, the four RF noise parameters and a wide range of figures-of-merit (FoMs). Finally, a discussion around inversion coefficient (IC) design methodology is carried out, where several FoMs based on IC are modeled with the use of very simple analytical expressions requiring only few parameters. Measurements of advanced 40 nm and 28 nm CMOS technologies are used throughout the thesis to validate all the different modeling approaches.