Conference paper

A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

In this paper, a die-level CMOS post-processing scheme for 3D integration using the via-last approach is presented for multi-layer stacking. The process includes TSV fabrication, chip-to-chip bonding, and finally the TSV filling with Cu electroplating. The proposed process flow is used to fabricate a 4-layer chip stack using homogeneous CMOS memory chips. Electrical measurements are carried out to determine the resistance value of the TSVs. Kelvin bridge method is used in order to eliminate the additional resistance introduced by the experimental setup, and the average resistance value of a single TSV is determined as 180 m Omega. The current carrying capability is also investigated for possible electrical failures. It is concluded that the TSVs can carry up to 1.5 A (DC) current values without any failure.


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