In this paper, an analytical noise calculation is presented to derive the impact of process and design parameters on 1/f and thermal noise for a low-noise CMOS image sensor (CIS) readout chain. It is shown that dramatic noise reduction is obtained by using a thin-oxide transistor as the source follower of a typical 4T pixel. This approach is confirmed by a test chip designed in a 180-nm CIS process and embedding small arrays of the proposed new pixels together with state-ofthe- art 4T pixels for comparison. The new pixels feature a pitch of 7.5 mu m and a fill factor of 66%. A 0.4e-rms input-referred noise and a 185-mu V/e-conversion gain are obtained. Compared with state-of-the-art pixels, also present onto the test chip, the rms noise is divided by more than 2 and the conversion gain is multiplied by 2.2.