An MIG-based Compiler for Programmable Logic-in-Memory Architectures

Resistive memories have gained high research attention for enabling design of in-memory computing circuits and systems. We propose for the first time an automatic compilation methodology suited to a recently proposed computer architecture solely based on resistive memory arrays. Our approach uses <i>Majority-Inverter Graphs</i> (MIGs) to manage the computational operations. In order to obtain a performance and resource efficient program, we employ optimization techniques both to the underlying MIG as well as to the compilation procedure itself. In addition, our proposed approach optimizes the program with respect to memory endurance constraints which is of particular importance for in-memory computing architectures.


Published in:
Proceedings of the 53rd Design Automation Conference (DAC)
Presented at:
53rd Design Automation Conference (DAC), Austin, Texas, USA, June 5-9, 2016
Year:
2016
Publisher:
New York, Ieee
ISBN:
978-1-4503-4236-0
Laboratories:




 Record created 2016-02-11, last modified 2018-03-17

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