A 1 x 400 Backside-Illuminated SPAD Sensor With 49.7 ps Resolution, 30 pJ/Sample TDCs Fabricated in 3D CMOS Technology for Near-Infrared Optical Tomography

A 1 x 400 array of backside-illuminated SPADs fabricated in 130 nm 3D IC CMOS technology is presented. Sensing is performed in the top tier substrate and time-to-digital conversion in the bottom tier. Clusters of eight pixels are connected to a winner-take-all circuit with collision detection capabilities to realise an efficient sharing of the time-to-digital converter (TDC). The sensor's 100 TDCs are based on a dual-frequency architecture enabling 30 pJ per conversion at a rate of 13.3 ms/s per TDC. The resolution (1 LSB) of the TDCs is 49.7 ps with a standard deviation of 0.8 ps across the entire array; the mean DNL is +/- 0.44 LSB and the mean INL is +/- 0.47. The chip was designed for use in near-infrared optical tomography (NIROT) systems for brain imaging and diagnostics. Measurements performed on a silicon phantom proved its suitability for NIROT applications.

Published in:
Ieee Journal Of Solid-State Circuits, 50, 10, 2406-2418
Piscataway, Ieee-Inst Electrical Electronics Engineers Inc

 Record created 2015-12-02, last modified 2018-01-28

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