A capacitance-voltage model for DG-TFET


Published in:
2015 Silicon Nanoelectronics Workshop (SNW), 1-2
Presented at:
IEEE Silicon Nanoelectronics Workshop, Kyoto, Japan, 14-15 June 2015
Year:
2015
Publisher:
IEEE, Piscataway, NJ, USA
Keywords:
Laboratories:




 Record created 2015-11-23, last modified 2018-09-13

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