Design optimization of polyphase digital down converters for extremely high frequency wireless communications

In this paper, an area-optimized polyphase digital down converter (DDC) architecture is introduced, where the mixers can be completely merged into the polyphase decimation filter under certain conditions. We also introduce an interface architecture, called synchronizer, between the back-end of an extremely high-speed time interleaved ADC (TI-ADC) and the front-end of a polyphase DDC. The synchronizer enables safe downsampling for a polyphase DDC, when the TI-ADC's sampling rate is above tens of GS/s. We show that the proposed interface architecture prevents any potential timing constraint violations that might occur in the interface between a TI-ADC and a polyphase DDC for extremely high frequency (EHF) wireless communication applications.


Published in:
Proceedings of 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 207-212
Presented at:
2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Daejeon, South Korea, October 5-7, 2015
Year:
2015
Laboratories:




 Record created 2015-11-11, last modified 2018-01-28


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