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Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture
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Layout Technique for Double-Gate Silicon Nanowire [...]
-
Bobba, Shasikanth
et al
main
file(s):
06918540
version 1
06918540.pdf
[5.03 MB]
27 Jan 2018, 12:38
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