A 7.5 Gb/s mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel with 45 dB loss at 2.5 GHz. The transmitted spectrum is composed of baseband (BB) and I /Q sub-bands with the ability to match the modulation frequency of the entire transceiver (TRX) with respect to the channel response over a +/- 25% range. A switched-capacitor-based mixer/filter is developed to efficiently down convert and equalize the I /Q sub-bands in the RX. The core size area is 85 x 60 um2 and 150 x 60 um2 for the TX and RX, respectively.