Well surface roughness and fault density effects on the Hall mobility of In[sub x]Ga[sub 1−x]As/In[sub y]Al[sub 1−y]As/InP high electron mobility transistors

In this work, we present a correlation between the morphological characterization of InyAl1−yAs/InxGa1−xAsheterostructures grown on InP substrates for high electron mobility transistors(HEMTs) applications as determined by transmission electron microscopy, and the electrical behavior of the two-dimensional electron gas(2DEG) confined in the InGaAs channel. Our main goal is to analyze the origin of the low and anisotropic values of 2DEGHall mobilities, discussing the effect of the density and asymmetric distribution of stacking faults and the surface undulation induced by a three-dimensional (3D) growth mode, depending on the growth temperature (Tg) and thickness (tw) of the InxGa1−xAs well. Our results have shown that a high mobility for a matched channel is obtained if the In0.53Ga0.47As layer is grown at 530 °C. Lower temperatures reduce the mobility values and lead to higher mobilities for [11̄0] due to the surface corrugation along [110] induced by lateral decomposition of the InGaAs at low growth temperatures. For HEMT structures with strained In0.75Ga0.25As channels grown at 530 °C, within the range of the well thickness considered (5–10 nm), Hall mobilities are also more influenced by the surface roughness than by fault distribution. However, in this case, the observed roughness is not driven by alloy decomposition but by a strain-induced 3D growth mode.

Published in:
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 15, 5, 1715

 Record created 2015-08-27, last modified 2018-09-13

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