Hardware-in-the-Loop Validation of an FPGA-Based Real-Time Simulator for Power Electronics Applications

This paper presents the hardware-in-the-loop (HIL) validation of a proposed FPGA-based real-time simulator for power electronics applications. The proposed FPGA-based real-time simulation platform integrates the Modified Nodal Analysis (MNA) method, Fixed Admittance Matrix Nodal Method (FAMNM) and an optimization technique to assess the optimal value of the switches conductance in order to minimize the relevant errors. Moreover, the proposed platform includes an automatic procedure to translate the netlist user-defined circuit schemes to the relevant equations to be solved in the FPGA. The proposed simulator is validated first by comparing the FPGA- based simulation results with offline ones performed by EMTP- RV. Then, further validation is presented by means of a dedicated HIL experimental setup composed of a controller connected to an actual two-level, three-phase inverter and its corresponding FPGA real-time model.


Editor(s):
Johnson, B. K
Published in:
Proc. of the 11th International Conference of Power Systems Transients (IPST), -, -, 1-7
Presented at:
11th International Conference of Power Systems Transients (IPST), Cavtat, Croatia, June 15-18, 2015
Year:
2015
Publisher:
Cavtat, Croatia, ipst.org
Keywords:
Laboratories:




 Record created 2015-06-17, last modified 2018-09-13

Publisher's version:
Download fulltext
PDF

Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)