Applying HTM to an OLTP System: No Free Lunch

Transactional memory is a promising way for implementing efficient synchronization mechanisms for multicore processors. Intel's introduction of hardware transactional memory (HTM) into their Haswell line of processors marks an important step toward mainstream availability of transactional memory. Transaction processing systems require execution of dozens of critical sections to insure isolation among threads, which makes them one of the target applications for exploiting HTM. In this study, we quantify the opportunities and limitations of directly applying HTM to an existing OLTP system that uses fine-grained synchronization. Our target is Shore-MT, a modern multithreaded transactional storage manager that uses a variety of fine-grained synchronization mechanisms to provide scalability on multicore processors. We find that HTM can improve performance of the TATP workload by 13-17% when applied judiciously. However, attempting to replace all synchronization reduces performance compared to the baseline case due to high percentage of aborts caused by the limitations of the current HTM implementation. Copyright 2015 ACM.


Published in:
DaMoN'15 Proceedings of the 11th International Workshop on Data Management on New Hardware, 7
Presented at:
The 11th International Workshop on Data Management on New Hardware, Melbourne, VIC, Australia, May 31 - June 04, 2015
Year:
2015
ISBN:
978-1-4503-3638-3
Note:
PUBLICATION_SHORE_MT
Laboratories:




 Record created 2015-04-23, last modified 2018-09-13

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