Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization

• Presented at: 25th Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, Pennsylvania, USA, May 20-22, 2015
• Published in: Proceedings of the 25th Great Lakes Symposium on VLSI (GLSVLSI), p. 39-44
• New York, NY, USA: ACM, 2015

As an answer to the new electronics market demands, semiconductor industry is looking for different materials, new process technologies and alternative design solutions that can support Silicon replacement in the VLSI domain. The recent introduction of graphene, together with the option of electrostatically controlling its doping profile, has shown a possible way to implement fast and power efficient Reconfigurable Gates (RGs). Also, and this is the most important feature considered in this work, those graphene RGs show higher expressive power, i.e., they implement more complex functions, like Majority, MUX, XOR, with less area w.r.t. CMOS counterparts. Unfortunately, state-of-the-art synthesis tools, which have been customized for standard NAND/NOR CMOS gates, do not exploit the aforementioned feature of graphene RGs. In this paper, we present a post-synthesis tool that translates the gate level netlist obtained from commercial synthesis tools to a more optimized netlist that can efficiently integrate graphene RGs. Results conducted on a set of open-source benchmarks demonstrate that the proposed strategy improves, on average, both area and performance by 17% and 8.17% respectively.

Keywords: graphene ; p-n junction ; reconfigurable gate ; synthesis ; optimization

Reference

• EPFL-CONF-207550
• doi:10.1145/2742060.2742098

Record created on 2015-04-23, modified on 2017-05-12