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conference paper
A 4x9 Gb/s 1 pJ/b NRZ/Multi-Tone Serial-Data Transceiver with Crosstalk Reduction Architecture for Multi-Drop Memory Interfaces in 40nm CMOS
2015
2015 Symposium on VLSI Circuits (VLSI Circuits)
An aggregated 36 Gb/s low power 4-lanes mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40nm CMOS technology. The proposed architecture achieves 1 pJ/bit power efficiency in the entire link (TX + RX) for an MDB channel with 45 dB loss at 3 GHz. The multi-tone nature of the proposed transceiver is employed to properly reduce crosstalk (Xtalk) induced noise and to improve overall power efficiency. © 2015 JSAP.
Type
conference paper
Publication date
2015
Published in
2015 Symposium on VLSI Circuits (VLSI Circuits)
ISBN of the book
978-4-86348-502-0
Start page
C180
End page
C181
Peer reviewed
NON-REVIEWED
EPFL units
| Event name | Event place | Event date |
Kyoto, Japan | June 15-19, 2015 | |
Available on Infoscience
March 11, 2015
Use this identifier to reference this record