In this paper, we analyze the 6T SRAM cell failures caused by temperature and supply voltage variations, and we explore the design of robust SRAM cells for high temperature operation. This integral SRAM reliability study is performed using 180nm SOI CMOS process transistor models. Three different operation regions are identified based on the temperature and supply voltage impact on failure rates. We show that in the superthreshold operation region failure rates increase with elevated temperatures while the opposite is true in the sub-threshold operation regions. We also provide physical interpretation of particularly interesting near-threshold operation region that demonstrated extremely high reliability and low failure rates. Further, we present reliability improvements of the 6T SRAM cell which lead to the fully-digital Latch based design. Silicon measurements demonstrate reliable, state-of-the-art, SRAM operation at 275 C (fMAX = 10MHz, PTOT = 400mW), that is by far the highest reported operating temperature for digital on-chip SRAM module.