Implementing super-efficient FFTs in Altera FPGAs

In this article, an alternative method is proposed to compute a fast Fourier transform (FFT) on Altera FPGAs. This method is using the Altera FFT intellectual property (IP) core, but it is more efficient than the direct use of the Altera FFT IP core, in the sense that the processing time or the resources can be reduced. For the FPGA user, the implementation of the proposed method is more complex than using directly the Altera FFT IP core because additional elements are required, such as a numerically controlled oscillator (NCO) or a memory, a complex multiplier, adders and scaling, but it may be worth it since the decrease in processing time or resources is significant, especially regarding the memory with large FFTs. The proposed method can also be applied to the computation of the convolution or correlation using FFTs.

EE Times Programmable Logic Designline
The Quartus II projects of the implementations mentioned in the paper, as well as ModelSim simulations and Matlab files used for the verification, are available through the following link : This article has been highlighted in the blog EE Times Programmable Logic DesignLine, by Max Maxfield. The post is available here.

 Record created 2015-01-12, last modified 2019-04-15

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