Majority-Inverter Graph for FPGA Synthesis

In this paper, we present an FPGA synthesis flow based on <em>Majority-Inverter Graph</em> (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. MIG manipulation is supported by a consistent algebraic framework leading to strong synthesis properties. We propose MIG optimization techniques targeting high-speed FPGA implementations. For this purpose, we reduce the depth of logic circuits via MIG algebraic transformations enabling denser LUT mapping on FPGAs. Experimental results show that our MIG-based design flow reduces by 21%, on average, the delay of the arithmetic circuits synthesized on a state-of-art 28nm commercial FPGA device, as compared to a commercial design flow.


Published in:
Proceedings of the 19th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2015), 165-170
Presented at:
19th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2015), Yilan, Taiwan, March 16-17, 2015
Year:
2015
Laboratories:




 Record created 2015-01-07, last modified 2018-03-18

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