Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading data from the processor pipeline. AVS creates coherence and consistence problems with the data cache. Although a hardware coherence protocol could solve the problem, this approach is costly for a single-processor system. As a low-cost alternative, we introduce Virtual Ways, which ensures coherence through a reduced form of inclusion between the data cache and AVS. Virtual Ways achieve higher performance and lower energy consumption than using a hardware coherence protocol.


Published in:
Acm Transactions On Architecture And Code Optimization, 11, 2, 3-28
Year:
2014
Publisher:
New York, Assoc Computing Machinery
ISSN:
1544-3566
Keywords:
Laboratories:




 Record created 2014-10-23, last modified 2018-03-17


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