A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory

The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag cost minimization. This paper presents the first low-cost, ultra-low power, passive RFID tag, fully integrated on a single substrate in a standard CMOS process. The system combines a 24 GHz, dual on-chip antenna, RF front-end, and a C-Flash based, rewritable, non-volatile memory module to achieve full on-chip system integration. The complete system was designed and fabricated in the TowerJazz 0.18 mu m CMOS technology without any additional mask adders. By embedding the RF, memory, and digital components together upon a single substrate in a standard digital process, the low-cost aspirations of the "5-cent RFID tag" become feasible. Design considerations, analysis, circuit implementations, and measurement results are presented. The entire system was fabricated on a 3.6 mm x 1.6 mm (6.9 mm(2)) die with the integrated antennas comprising 82% of the silicon area. The total read power was measured to be 13.2 mu W, which is sufficiently supplied by the on-chip energy harvesting unit.

Published in:
Ieee Journal Of Solid-State Circuits, 49, 9, 1942-1957
Piscataway, Institute of Electrical and Electronics Engineers

 Record created 2014-10-23, last modified 2018-12-03

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